Forum Discussion
Occasional ContributorNCSIM of PLLs not generating correct output frequency
Aqid, no simulation error just the waveform frequency is incorrect. I modified the PLL to accept 104MHz but on the input I changed to multiple by 7 and divide by 2 and then changed my output stages to account for the VCO frequency difference to get the right frequencies I needed. This does simulate properly and generates the correct clocks. I cannot explain it but this was my solution and I am moving forward.
Occasional ContributorAqid, no simulation error just the waveform frequency is incorrect. I modified the PLL to accept 104MHz but on the input I changed to multiple by 7 and divide by 2 and then changed my output stages to account for the VCO frequency difference to get the right frequencies I needed. This does simulate properly and generates the correct clocks. I cannot explain it but this was my solution and I am moving forward.
