Forum Discussion
ThomasTessier
Occasional Contributor
Occasional ContributorNCSIM of PLLs not generating correct output frequency
QuartusPrime 21.1 on CentOS7. Arria5 GX.
I have a PLL which accepts 104MHz (from an upstream) and is suppose to generate 182MHz and 91MHz. That is a multiply by 7 with a divide by 8 and divide by ...
Aqid, no simulation error just the waveform frequency is incorrect. I modified the PLL to accept 104MHz but on the input I changed to multiple by 7 and divide by 2 and then changed my output stages to account for the VCO frequency difference to get the right frequencies I needed. This does simulate properly and generates the correct clocks. I cannot explain it but this was my solution and I am moving forward.
AqidAyman_Altera
Regular Contributor
Regular ContributorHello Tom,
Thank you for reaching out Intel FPGA Community.
Do you face the simulation error? It is very appreciated if you can share any snapshot or message error that can describe more the issue that you are facing.
Regards,
Aqid
