Forum Discussion
Altera_Forum
Honored Contributor
14 years agoHi,
I am also doing demux for the RX port and there is no error with that. Doing something like this.. always@(posedge clk) begin if(owner==1'b1) begin rx_data_0 = mac_rx_data_1; . . . tx_ready_0 = mac_tx_ready_1; end else begin rx_data = mac_rx_data_1; . . . tx_ready = mac_tx_ready_1; end end Tried the same structure of always @(posedge clk) with TX but having same errors. Synthesis stops after the error. thanks sawaak