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Altera_Forum's avatar
Altera_Forum
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16 years ago

Multiple UART instantiation

We have a customer that needs 12 UARTS in his design. Is there a UART core that we can instantiate 12 times in a relatively inexpensive FPGA?
Altera_Forum's avatar
Altera_Forum
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16 years ago

A simple UART (with parity) needs e.g. about 70 logic cells for RxD and 32 for TxD, in addition some logic cells for a baud rate divider, that can be shared by all UART instances. It's just some lines of VHDL code written from the scratch. You'll also find a simple UART design a opencores http://www.opencores.org/projects.cgi/web/uart/overview, some examples have been previously posted at alteraforum.