New Contributor
Regular ContributorHi,
As I understand it, you have some inquires related to the TX PLL placement. To facilitate further debugging, it is recommended for you to create simple test design with only Native PHY instances mimic the configuration used by the IP ie data rate, bonding, refclk and channel placement. This would help to isolate out IP dependencies ie TSE, XAUI from the debugging. You may start with simple design ie one x4 Native PHY, then slowly add on more modules and test the compilation. This will be helpful to narrow down when the error start to pop up. Please feel free to share with me the Native PHY only test design which is able to replicate similar placement error so that I could further look into it.
Please let me know if there is any concern. Thank you.
