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Altera_Forum's avatar
Altera_Forum
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15 years ago

multichannel FIR output timing error

When I use multichannel fir filter, the timing of output channels is not correct. The output generated by 1 channel shifted. For example, First channel data filtered out to second channel, second ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Did either of you find a solution to your problem?

I have a two channel filter but have only been putting signals into channel 0. I have been debugging a DC block module. Eventually I decided there was a timing issue on the input (output of the FIR). With a bit of messing I found the signal appears on channel 1.

Is this the same as what you are seeing?

I have to make a few hardware modifications to my test boards before I can stuff a signal into channel 1.

my dc block simulates ok. I use Altium Logic Analyser (which is the same as signal tap, i think).

any advice?

Quartus 9.2, 2 channel, decimating by 8, parrallel

update- I have connected channel 0 and it seems that the output is swapped. That is, I is on channel 0 and Q is on channel 1, feeds the FIR. The output is Q channel 0 and I on channel 1.

The actual filtering and data signals are fine.

I have probably crossed my Is and Qs somewhere. I shall recheck the input to the FIR, but the output is definitly as above.