Honored Contributor
Honored ContributorI don't have enough experience to address your specific case, but I can share some experiences I have had.
I've got a project on the Cyclone V (non SoC, but I'm going that direction next most likely) using the arrow BMCV board. This board has a 16 bit memory interface to the hard memory controller and it runs at 333 MHz if my memory serves me correctly. In my design I've got a MPFE with a 32 bit wide port going to a jtag bridge and a 128 bit wide port fed from my logic running burst length of 128 and I achieved about 80% of my calculated efficiency. I think I calculated that if there was no overhead for calibration or anything else that you could get 10.6Gbits/sec and after a lot of testing up and down I almost always had a hard failure at 80% of this (I varied clock and burst length). n my case the burst length seemed secondary, but to keep the overhead down bursting really does seem to make sense. It took me a while (and some help from an FAE) to get all of the avalon signals managed correctly. There's a KB article that hints at a possible explanation of the 80% in my case, but I never got a confirmation (it talks about losing a cycle due to scheduling every four cycles or something like that, but it doesn't really add up. I had really hoped to get into the low 90's but never figured out what the problem was so I had to alter my approach. I ran into similar issues with the FIFO resources. I did use beginbursttransfer in my design. So I guess I would expect you to be able to get a much higher efficiency in yours. In mine since one port is basically idle and the other port is as wide as I can make it with long bursts, I'm not sure it is a fair comparison. I have really only scrutinized the write bandwidth; I read it out much slower, but I'm constantly writing. -Lance
