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Altera_Forum's avatar
Altera_Forum
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15 years ago

Multi-master arbitration

Hi, I have a complex SOPC system with a number of video processing blocks requiring access to DDR2 memory provises by a single HPC DDR2 memory controller. The memory master interface can be d...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi,

Wow! Impressive reference design - I have not seen this one before. I am first going to try to make my own arbitrator since I think it should be fairly simple in my case. But I'll keep this one in mind. Problem with many reference designs are that they do show the full capabilities of the cores / system, but they are typically not commercially viable. I have to do a very similar task than in this reference design, but in a mid range CIII (up to 1080i) - and the customer is already not too happy about the cost of the FPGA. Had to re-write a couple of the standard cores to be specifically efficient for my purpose. Trade development time for lower production cost.

Regards,

Niki