Multi clock verilog hdl design and hdl import

Hello

According to the documentation on the hdl import block in DSP builder, any multi clock hdl designs will result in one clock being used as the implicit clock and additional clocks will be represented as ports on the simulink block.

I am importing a dual clock verilog hdl design, the compilation performs succesfully but the second clock is not represented in the simulink block.

Is the documented feature restricted to VHDL? or do i need to format my verilog code in any particular way in order for the second clock to be shown on the simulink block?

Best regards

Jesper Kristensen