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Me too, actually. The reply was basically that there was a bug. If you read the release notes for Quartus, it sounds like the FIFO reset bug is fixed. I haven't tested it though as I built a workaround in RTL to manage the FIFO bug. The mSGDMA has been working pretty well.
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Thanks. Not sure what is the issue that I'm running into then. When I set the reset bit in the control register, it clears itself automatically, but the resetting bit in the status register never gets deasserted. The whole thing hangs up, stuck in a resetting state.