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After consulting with Altera support, the mSGDMA core does have a bug and slightly different operation from the manual. According to them, the SW_RESET bit needs to be set and then cleared BY SOFTWARE to correctly reset, due to some bugs in the FIFO resets. This means that the reset bit doens't automatically return to zero to indicate a reset complete when in certain states. I can post the Altera support reply if anyone is interested. Hopefully the IP core bug and documentation can be synchronized.
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I know it's an year later, but I'd appreciate the Altera support reply.
Honored Contributor
