Module dependency loop warning???

Just for background, I have a subsystem (let's call it subsys.qsys) which contains my HPS block and some peripherals, one of them being a clock_bridge component. This bridge brings the mm_bridge_0_clk port from the HPS up to the next level.

In my main system (lets call it sys.qsys) I bring in the subsystem and I distribute that bridged clock output to more peripherals and some custom IP, including another clock_bridge to further bring that clock up to the top level project .v file.