Module avalon mm slave and master

Hi leobenedette,

Would you mind to further clarify if you are looking for any specific application's AVMM master and slave? You could try to search through the Altera wiki page for embedded design example to see if can find any specific design example that suit you:

http://www.alterawiki.com/wiki/category:embedded_design_examples

http://www.alterawiki.com/wiki/category:embedded_hardware_and_hardware_tools

http://www.alterawiki.com/wiki/category:embedded_processing

http://www.alterawiki.com/wiki/category:embedded_software_and_software_tools

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I need a example of a module avalon mm that is master and slave.

Or how can I build one.

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As I understand it, the transceiver toolkit design example is always using JTAG master to interface with other slaves through AVMM. Probably you could try to have a look on how the design is constructed in Qsys to get further idea.

You can get the design examples at https://www.altera.com/content/dam/altera-www/global/en_us/others/support/examples/download/transceiver_toolkit_13_0sp1_qar.zip

hi leobenedette,

You could try to search through Altera wiki (http://www.alterawiki.com/wiki/special:categories) and Altera ref design page (https://www.altera.com/products/intellectual-property/reference-designs.html) to see if can find any design for reference.

You can try to look at Avalon-MM master & slave template :-

https://www.altera.com/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-avalon-memory-slave.html

https://www.altera.com/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-avalon-mm.html