Modular SGDMA - Streaming to Memory Mapped Random first write.

TCWORLD,

So I was able to implement your code, however I still get the same result: The DMA descriptor FIFO fills up and then stays filled - so no descriptors are actually being executed.

Let me outline my system (maybe I'm making a fundamental error):

The goal is to transfer streaming data into the SDRAM chip on the DE0 Nano board. I want the code (.text,.heap,.stack, all of it) and the descriptors to be held in on - chip memory, while the streaming data is saved on sdram.

Therefore, in my linker script in the BSP setup, everything is set to onchip memory.

In qsys, the data_write_master from the dma_write_master module is connected to the s1 port on SDRAM. The nios data and instruction masters are connected to onchip memory, and the data master is also connected to sdram s1 port for a way to read data for testing purposes.

So essentially, code and descriptors are on onchip memory, data should be saved to sdram via msgmda.

For some reason, when I used the C functions provided with the msgdma and when I used you ScatterGatherController files, I got the same result of the descriptor FIFO filling up, but no data actually being saved.

My data (for testing purposes) is currently a counter that increments every N number of clock cycles (N = 1000). So the data rate is 50MHz (base clock) / 1000 = 50kHz. Every N clock cycles a valid signal is triggered.

I can't find an issue, I've tried various combinations of burst vs. non bust, full word vs. aligned options, etc. No change in results. Let me know, if I'm missing something really obvious, or if you think of some reason that can be causing this issue. It would help a lot.

Thanks!!