Modular SGDMA - Streaming to Memory Mapped Random first write.

I think I have worked out the problem. In the fifo_with_byteenables module in the dispatcher, there are MLAB cells inferred for the FIFO. Each of these has a byteenable, but they are registered inputs. If the Avalon-MM interconnect to the descriptor input sets up the byte enable signal at the same time as the write signal, the write is going to reach the MLAB cell one clock cycle before the byte enables reach it (because they are pipelined). If I am not mistaken this means that the MLABs will write the data before it is properly masked causing corruption.