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Altera_Forum
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11 years ago

Modular SGDMA - Streaming to Memory Mapped Random first write.

Hi, I am using the Modular SGDMA to write memory into DDR3 memory, and then a second one to read it back out again. The reading is all working fine and writing into the memory works as well, ex...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Interestingly, despite the fact I have the 'Length' parameter set to 512MB, Quartus synthesizes away bits [31:16] of the length signal in the descriptor FIFOs.

EDIT:

QSys for some reason put a length signal width of 16 in the generated source file instead of 30. I've tried regenerating the QSys system, but each time it sets the 'LENGTH_WIDTH' parameter on the write_master to 16?!? Is this a glitch in QSys?