Honored Contributor
Honored ContributorI've been doing some tests and can see that the following work:
(1) NIOS generates descriptor (not using supplied driver). (2a) First 32 bit is written to controller (read address) - this is set to zero as it is a write controller and doesn't matter. Byte Enable = 0x000F (2b) Second 32 bit chunk of descriptor written (write address) - trying say 64 (which is an aligned address). Byte Enable = 0x00F0 (2c) Third 32 bit is written (length) - this is set to 0x480000 which is how much I want to transfer. Byte Enable = 0x0F00 (2d) Fourth 32 bit word written. I have bits 8,9,12,24 and 31 set. Byte Enable = 0xF000 - All of those transactions have been checked in signaltap and I can see the correct data and byte enables being sent along with the write signal being asserted correctly. (3) I can see the SGDMA dispatcher issue the write descriptor, but it seems that the data that gets sent to the write master via the write commands source port is basically just a whole lot of 1's (apart from the 'park writes' and 'transfer complete IRQ' bits which are 0). For clarification I have the following settings for the IP core: Streaming to MM Packet Support = Disabled Max Write Length = 512MB Descriptor FIFO = 8 Data FIFO = 64 Burst Count = 16 Forced Burst Alignment = True Burst Enable = True Transfer Type = Full Word Accesses Only Data Width = 512 Response Port = Disabled. No idea why the dispatcher is turning my descriptors into garbage when the descriptors bus at the input is presenting the correct data/control signals.
