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Altera_Forum
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12 years ago

Modify Ariia V ALTLVDS_TX data rate during work

Hello everyone, I'll try to explain the issue as clear as I can. I have a block which can operate at 2 different clock rates : 162 MHz and 270 MHz. I need to use ALTLVDS_TX with serialization ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hello all, I am trying to constrain my ALTLVDS design on Cyclone V which is using the same SERDES as ARRIA V. I get littre channel to channel skew and I want to correct it. In the fitter report there is the LVDS receiver package skew compensation and the LVDS Transmitter Package Skew Compensation. How to add the trace delay addition recommended in those report ? I didn't find any hints on the web fix it.

Thank you for your help.