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Altera_Forum's avatar
Altera_Forum
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12 years ago

Modify Ariia V ALTLVDS_TX data rate during work

Hello everyone, I'll try to explain the issue as clear as I can. I have a block which can operate at 2 different clock rates : 162 MHz and 270 MHz. I need to use ALTLVDS_TX with serialization ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

"Are you trying to send data out at 1620 Mbps and 2700 Mbps, while inside the FPGA you have 10 bit words of 162Mbps or 270 Mbps?"

This is exactly the case! :)

If LVDS won't work , what solution do you suggest?