Forum Discussion
Thanks for answer.
You are right, the problem is with the paths.
I changed the lines as follows:
eval vlog $ USER_DEFINED_VERILOG_COMPILE_OPTIONS $ USER_DEFINED_COMPILE_OPTIONS "$ QSYS_SIMDIR /../../ main.v"
eval vlog $ USER_DEFINED_VERILOG_COMPILE_OPTIONS $ USER_DEFINED_COMPILE_OPTIONS "$ QSYS_SIMDIR /../../ AC_meas_tb.v"
Now all modules are compiled without errors after command:
source msim-setup.tcl,
ld,
but an error is thrown at the end:
# vsim -t ps -L work -L work_lib -L onchip_flash_0 -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver AC_meas_tb
# Start time: 09:02:11 on Feb 27,2020
# ** Error: (vsim-3170) Could not find 'AC_meas_tb'.
# Searched libraries:
******
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./AC_meas_NIOS_run_msim_rtl_verilog.do PAUSED at line 24
I do not understand which "AC_meas_tb" the simulator does not find.
PS If I start RTL simalation from Qaurtus I get error "Error: (vsim-3033): Instantiation of 'altera_onchip_flash_block' failed".