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Thanks, I manage to look into it.
Since the design are from qsys, what you need to run is msim_setup.tcl. You may follow the steps below:
1) Open up the qsys files, generate the simulation model, generate -> generate hdl
2) Open modesim, cd to directory where the msim_setup.tcl
source msim_setup.tcl
3) ld
4) now the modelsim success run the simulation.
to include the tb
5) open up the msim_setup.tcl and modify the top level to spi_flash_tb
6) make sure your spi_flash_tb.vhd spi_flash under vcom
7) ld again.
Let me know if you do not get it,
Thanks
- AFahr26 years ago
New Contributor
Kenny, thanks for your answer, it took me a while but I got it in the end.
Just for the sake of completion if anyone runs into the same issues:
- The msim_setup_tcl file is located under /simulation/mentor
- I replaced the original testbench file with my "spi_flash_tb.vhd" file on this line: "set TOP_LEVEL_NAME "spi_flash_tb" "
- I added the following lines under vcom, at the end, in this order:
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/rsu_test.vhd"
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/spi_flash.vhd"
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/spi_flash_tb.vhd"
Otherwise the test simulation was missing some blocks.
- Ran the following commands:
quit -sim
source msim_setup.tcl
ld
and it all seems to compile now. I'll test it for a while now, but it seems the issues I was having are resolved.
Thanks kindly for your support!
Cheers,
Albert F.
- Stephanie5 years ago
New Contributor
Hi Albert I'm running into the same issue as you, what does your altera_onchip_flash_block.v look like? Mine is a hex file it seems...