Memory port limits on Stratix V

AFAIK the only way to create more than 2-port rams is by using HDL code.

Do you need all your ports to have read and write access? In that case you can't use the embedded RAM blacks and the synthesizer will infer registers. This will use a lot of memory to compile the design and use a lot of resources on the FPGA if your memory block is big.

If you only have one port with write access then in theory it is possible to implement the function using several dual port blocs in parallel, but I don't think the synthesizer will do that automatically for you. You'll probably have to do it manually in your HDL code.