Honored Contributor
Honored ContributorHi, angryconsumerism,
A testbench is automatically generated when you instantiate a FFT core (in DSP Builder or Quartus). Perhaps taking a look at the generated test bench might give you a better idea... I will try to de-cipher it for you a bit: - Your 50 MHz clock would go into the clock input port and nothing else... - sink_sop and sink_eop: these are start and end of packets signals for your inputs... you would have to code a FSM that generates these signals for you... - sink_valid -> DO NOT just set this to high... the signal is used to tell FFT whether inputs are valid or not... you might want to check with sink_ready (an output signal)... - source_ready -> you would have to assert/de-assert this signal, to let the FFT know whether the downstream modules are ready for outputs or not... - source_eop, source_sop, source_valid: these are output signals that you do not have to set yourself... Of course it depends on what architecture you are trying to use... if you tell me more about your FFT, I might be able to help you more.... Good luck!
