Forum Discussion
Hi,
Thanks for reaching again.
- Do you try to run the example design without modification ? is it behave the same ?
- What kind of payload size you are using to do the test
- Did you develop your own driver or you are using our example design driver ?
- Did you capture the below signals to check if the data is mismatch or not ?
pcie_ed_tb.pcie_ed_inst.dut.dut.ast.p0_rx_st_valid_o[1:0]
pcie_ed_tb.pcie_ed_inst.dut.dut.ast.p0_rx_st_data_o[511:0]
pcie_ed_tb.pcie_ed_inst.dut.dut.ast.p0_rx_st_ready_i
pcie_ed_tb.pcie_ed_inst.dut.dut.ast.p0_rx_st_hdr_o[255:0]
pcie_ed_tb.pcie_ed_inst.dut.dut.ast.p0_rx_st_sop_o[1:0]
pcie_ed_tb.pcie_ed_inst.dut.dut.ast.p0_tx_st_data_i[511:0]
pcie_ed_tb.pcie_ed_inst.dut.dut.ast.p0_tx_st_eop_i[1:0]
pcie_ed_tb.pcie_ed_inst.dut.dut.ast.p0_tx_st_sop_i[1:0]
pcie_ed_tb.pcie_ed_inst.dut.dut.ast.p0_tx_st_ready_o
pcie_ed_tb.pcie_ed_inst.dut.dut.ast.p0_tx_st_valid_i[1:0]
pcie_ed_tb.pcie_ed_inst.dut.dut.ast.p0_tx_st_hdr_i[255:0]
Looking forward to hear back from you.
Regards,
Wincent_Intel
I'm uploading a report showing the results of our tests for 64 channels and 65 channels using the example design with settings for 256 channel support. Also, the example design driver is used.
regards,
Greg
- Wincent_Altera3 years ago
Regular Contributor
Hi @grspbr ,
If refer to the user guide, there is a 1.2. Known Issues
Where if setting Multichannel D2H AVST configuration has stability issues when total number of D2H channels configured is greater than 256. Please consider this in your design.Also, if refer to 3.1.6.1. Avalon-ST 1-Port Mode
- In the current Intel® Quartus® Prime release, the D2H Prefetch Channels follows the total number of DMA channels that you select up to 256 total channels.
- When the total number of channels selected is greater than 256, then D2H Prefetch channels are fixed to 64.
- The resource utilization shall increase with the number of D2H prefetch channels.
- For details about these parameters, refer to the 4.12.2. D2H Data Mover Interface
Hope this answer your question.
Regards,
Wincent_Intel
- grspbr3 years ago
Occasional Contributor
Note that we are not exceeding 256 channels. We are trying to use more than 64 channels though. When we try 65 channels, for example, we get a hang up in the PC. We think that the 64 limit on descriptor prefetch may not be handled properly, either in our code or the example driver so we are looking at that right now.
regards,
Greg
- Wincent_Altera3 years ago
Regular Contributor
Hi,
Yes, you are correct. there is limit on descriptor prefetch as per stated in the user guide.
Please consider it in your design .Regards,
Wincent_Intel