Occasional Contributor
Regular ContributorHi,
Thanks for reaching again.
pcie_ed_tb.pcie_ed_inst.dut.dut.ast.p0_rx_st_valid_o[1:0]
pcie_ed_tb.pcie_ed_inst.dut.dut.ast.p0_rx_st_data_o[511:0]
pcie_ed_tb.pcie_ed_inst.dut.dut.ast.p0_rx_st_ready_i
pcie_ed_tb.pcie_ed_inst.dut.dut.ast.p0_rx_st_hdr_o[255:0]
pcie_ed_tb.pcie_ed_inst.dut.dut.ast.p0_rx_st_sop_o[1:0]
pcie_ed_tb.pcie_ed_inst.dut.dut.ast.p0_tx_st_data_i[511:0]
pcie_ed_tb.pcie_ed_inst.dut.dut.ast.p0_tx_st_eop_i[1:0]
pcie_ed_tb.pcie_ed_inst.dut.dut.ast.p0_tx_st_sop_i[1:0]
pcie_ed_tb.pcie_ed_inst.dut.dut.ast.p0_tx_st_ready_o
pcie_ed_tb.pcie_ed_inst.dut.dut.ast.p0_tx_st_valid_i[1:0]
pcie_ed_tb.pcie_ed_inst.dut.dut.ast.p0_tx_st_hdr_i[255:0]
Looking forward to hear back from you.
Regards,
Wincent_Intel
Occasional ContributorHi @Wincent_Altera , thanks for the reply,
we used the example design originally without modification and it was working, with both example driver and our driver.
Then we removed the packet generator/checker from the example to create our own design which also worked with both our driver and example design driver.
Then we tried to modify the MCDMA/PCIE core to 256 channels from 64, and this is where we start having problems. We used payloads of 8K for the 64 channel case, and 2K for the 256 channel case.
Why does the example design only use 64 channels? Why not 256 or the max 2K?
We are now in the process of trying the example design customized for 256 channels. We will try to get reports from the example driver to you.
We do monitor those signals in our design with signaltap but do not yet have a capture when it fails, but we'll keep trying.
regards,
Greg
Occasional ContributorI'm uploading a report showing the results of our tests for 64 channels and 65 channels using the example design with settings for 256 channel support. Also, the example design driver is used.
regards,
Greg
Regular ContributorHi @grspbr ,
If refer to the user guide, there is a 1.2. Known Issues
Where if setting Multichannel D2H AVST configuration has stability issues when total number of D2H channels configured is greater than 256. Please consider this in your design.
Also, if refer to 3.1.6.1. Avalon-ST 1-Port Mode
Hope this answer your question.
Regards,
Wincent_Intel
Occasional ContributorNote that we are not exceeding 256 channels. We are trying to use more than 64 channels though. When we try 65 channels, for example, we get a hang up in the PC. We think that the 64 limit on descriptor prefetch may not be handled properly, either in our code or the example driver so we are looking at that right now.
regards,
Greg
