maximizing read bandwidth of HP DDR2 memory controller

It's no problem to come near to theoretical RAM bandwidth performing full row accesses, as kest mentioned. I understand, that the present problem is in reading smaller quantities concurrently. My understanding is, that the HP controller is keeping the state for each individual memory page in the RAM array, so the answer to briane's last question would be yes. But I didn't yet test HP performance in switching open pages and am not aware of available options to optimize the behaviour in this regard.