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Altera_Forum
Honored Contributor
16 years agoIt depends on a few factors, and I'm not sure you can get a constant value for this.
Like you mentioned, Nios II frequency and instruction cycles play a role. You can also look at the latency from the PIO, which I believe is 1 cycle. Next is the system architecture. The arbitration within the bus will affect the latency of data coming back. Your best bet is to use tightly-coupled memories for the CPU data and instruction, have direct connections to your PIO without going through bridges, etc.