matrix operation in vhdl

I notice several problems here:

1. arrays have to be declared like this:

type some_array_t is array(a to b, c to d) of integer; --downto can be used instead of to

so for you, you need

type matrix is array(row'low to row'high, column'low to column'high) of integer;

2. You cannot have variables in an architecture. Variables only belong in processes, functions or procedures. You must use signals instead (you can use shared variables, but DONT go there until you know what you're doing).

3. You dont need to declare i and j, they are declared when you create the loop.

I also notice with your code, nothing is connected to any inputs or outputs, is this intentional. What is your intention? to create synthesisable code or some testbenching code?