matrix operation in vhdl

This is the code i write and actually i want to has a matrix transpose from row to column.

library ieee;

use ieee.std_logic_1164.all;

entity transpose is

port (

-- Inputs

in1 : IN integer RANGE -127 TO 127;

in2 : IN integer RANGE -127 TO 127;

in3 : IN integer RANGE -127 TO 127;

--Outputs

out1 : OUT integer RANGE -127 TO 127;

out2 : OUT integer RANGE -127 TO 127;

out3 : OUT integer RANGE -127 TO 127;

end transpose;

architecture transpose of transpose is

type column is range -127 to 127;

type row is range -127 to 127;

type matrix is array (row,column) of integer;

variable prod : matrix;

variable i,j : integer;

begin

process

begin

for i in -127 to 127 loop

for j in -127 to 127 loop

prod (i,j)<= prod (j,i);

end loop;

end loop;

end process;

end transpose;

I think the error is at the array structure.Can you tell me what am wrong?

Many thanks