Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

master write done signal high on startup

Hi, I designed a Verilog unit which interacts with the SDRAM by means of two Avalon MM Master Templates (which I just abruptly downloaded and added to my Sopc builder Nios System after adjusting my c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

the reset_n port is connected to one of the DE1 pushbuttons, but I didn't connect the ports inside of SoPC Builder because if I do I get a warning about some "global reset" that makes the connection redundant.