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Altera_Forum
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15 years ago

master write done signal high on startup

Hi, I designed a Verilog unit which interacts with the SDRAM by means of two Avalon MM Master Templates (which I just abruptly downloaded and added to my Sopc builder Nios System after adjusting my c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I think the reset ports should be connected. How are those signals generated in your code?