ymiler
Contributor
ContributorLVDS SERDES IP
Hi
I have task to transmit data from 1 board to another
Each board has FPGA stratix 10M
To do it - I use LVDS SERDES IP in FPGA (TX) and other LVDS SERDES IP in FPGA (RX)
All the pins define as LVDS (including clocks & data)
My problem is : Sometimes pll lock flag doesn't lock
I don't know what is root casue for that - but I sample the clocks by scope
You can find it in the attached pic :
Do I need change the IO standard ?
Do I need change the internal termination ?
BR,
Yishay
