ymiler
Contributor
ContributorLVDS SERDES IP
Hi
I have task to transmit data from 1 board to another
Each board has FPGA stratix 10M
To do it - I use LVDS SERDES IP in FPGA (TX) and other LVDS SERDES IP in FPGA (RX)
All the pins d...
Forum Discussion
ymilerContributor
ContributorHi
Do you know what could be the reason for the unstabilty lock ?
Each reset / PWR on/off or FPGA loading get another lock flag value from the SERDES IP port
Yishay
