Occasional ContributorLVDS SERDES IP with cascaded downstream PLL
Hello,
I have a question about cascaded downstream PLLs.
I created a LVDS SERDES core with internal PLL.
I selected an additional output to use this clock as a PLL refclk input for my downstream PLL.
Is this a valid connection to get the clock from SERDES as upstream PLL to connect a downstream PLL?
I've connected the locked-output to the permit_cal-input of the downstream PLL.
Furthermore I've connected the additional clock output to the adjpllin-input.
Downstream PLL has High-Bandwidth setting, of course.
During Fitter (Plan - stage) I receive this critical warning:
Critical Warning: Could not find PLL ref clock that feeds io_pll|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll|outclk[0]
Furthermore I saw this info:
Info(18386): io_pll|stratix10_altera_iopll_i|outclk[0] (1824 fanout) drives clock Sectors (4, 3) to (6, 3)
and checked the PLL Usage Summary for this downstream IO PLL where the pll_cascade_in is detected correctly:
-- PLL_CASCADE_IN source:
rx_lvds_serdes|core|arch_inst|pll_inst|internal_pll|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll
I really want to take care that there is no issue in the connection and try to avoid any critical warnings in my design.
Could you maybe help me to find the reason for this critical warning and how to avoid it?
Is there any issue in my connection from SERDES LVDS (internal PLL) to downstream IO PLL?
Best regards,
Michael
Hi Michael
Thanks for your inquiry.
In general, we don't use output clocks from LVDS SERDES IP as the purpose to cascade another PLL. Are you creating your design using Platform Designer?
In Platform Designer, I don't see a valid connection from output clocks of LVDS SERDES IP to the adjpllin of the cascaded PLL, in fact, the connection from cascade_out of an upstream PLL to the adjpllin of downstream PLL is available.
Thanks.
Eng Wei
