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MichaelB's avatar
MichaelB
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

LVDS SERDES IP with cascaded downstream PLL

Hello, I have a question about cascaded downstream PLLs. I created a LVDS SERDES core with internal PLL. I selected an additional output to use this clock as a PLL refclk input for my downstre...
  • EngWei_O_Intel's avatar
    EngWei_O_Intel
    5 years ago

    Hi Michael

    Thanks for your inquiry.

    In general, we don't use output clocks from LVDS SERDES IP as the purpose to cascade another PLL. Are you creating your design using Platform Designer?

    In Platform Designer, I don't see a valid connection from output clocks of LVDS SERDES IP to the adjpllin of the cascaded PLL, in fact, the connection from cascade_out of an upstream PLL to the adjpllin of downstream PLL is available.

    Thanks.

    Eng Wei

EngWei_O_Intel's avatar
EngWei_O_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi Michael

Thanks for your inquiry.

In general, we don't use output clocks from LVDS SERDES IP as the purpose to cascade another PLL. Are you creating your design using Platform Designer?

In Platform Designer, I don't see a valid connection from output clocks of LVDS SERDES IP to the adjpllin of the cascaded PLL, in fact, the connection from cascade_out of an upstream PLL to the adjpllin of downstream PLL is available.

Thanks.

Eng Wei

  • MichaelB's avatar
    MichaelB
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hi! Thank you for your reply!

    Yes I was using the platform designer. I just thought I can connect a downstream PLL due to info in SERDES LVDS IP that a downstream PLL should have High Bandwidth setting. I assumed I can connect an additional outclk to adjpllin and the locked to the permit_cal signal (like general IO PLL cascading).

    Now I have created an external PLL which is connected to the LVDS SERDES block and use a cascade-out from external PLL for my downstream PLL.

    Using this connection there is no critical warning in my design and fitter result shows all clocks which I have configured.

    Best regards,

    Michael

    • EngWei_O_Intel's avatar
      EngWei_O_Intel
      Icon for Frequent Contributor rankFrequent Contributor
      5 years ago

      Hi Michael

      Great that the issue is going away and I hope this suit your design needs. I am currently transitioning this case to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

      Eng Wei