Forum Discussion
7 Replies
- Altera_Forum
Honored Contributor
What do you mean by 'latency'?
I guess that the delay between the time some data is received on the MII interface and the time when it is available on the stream interface for a TSE MAC is quite small and constant. But if you add the latency due to the software part, until the data is available at the UDP or TCP level will be quite higher, and will depend on the OS, IP stack and driver used. This latency could be reduced by using some hardware acceleration/implementation of the higher level of the stack. - Altera_Forum
Honored Contributor
Like you says. I mean the "delabetween the time some data is received on the MII interface and the time when it is available on the stream interface"
- Altera_Forum
Honored Contributor
In that case I don't think that you'll see a big difference between MACs. With the TSE you can remove the FIFOs to reduce it, but you'll still have a few cycles of latency due to clock domain crossing logic.
- Altera_Forum
Honored Contributor
Ok, thank you.
In xilinx fpga there are hard coded mac. Does it mean that there is less latency ? Shalom - Altera_Forum
Honored Contributor
i mean less latency than TSE ?
- Altera_Forum
Honored Contributor
I don't think so. But what is your problem exactly? Is the TSE's latency that high?
- Altera_Forum
Honored Contributor
No no,
I m just looking for a MAC with a minimum latency. Shalom