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Altera_Forum
Honored Contributor
Honored ContributorLooking for advice on large FIFO implementation
Hello, I'm planning to implement a kind of ethernet-to-parallel data link using a 3C120 dev kit. The idea is to get the data from ethernet, using something similar to the UDP off-load example, ...
Altera_ForumHonored Contributor
Honored ContributorUp on www.altera.com is a design example called the "Master Templates". You could take a look at those to learn more. Some of the logic you will not need since your addressing scheme doesn't need to be as complicated. Since the new DDR SDRAM controllers don't require bursting to be efficient I would recommend creating a non-bursting read/write master since it's a little bit easier to implement.
