Looking for advice on large FIFO implementation

Actually this should be easier to implement than trying to use DMAs to do it. Really all you need is a master that keeps track of a read and write address independently and makes sure they the addresses never cross. You would implement the counters to be modulo so that they can roll over and start at the beginning of the memory where appropriate. I would also use some on-chip memory FIFOs to buffer between the master and the streaming inputs and outputs of the FIFO block.

So for the FIFO input I would do something like this:

ST Data Input (sink) --> Onchip FIFO --> Write Master (to SDRAM)

For the FIFO output I would do something like this:

Read Master (from SDRAM) --> Onchip FIFO --> ST Data output (source)

Those Onchip FIFOs allow you to use the empty/full signals to implement ST flow control and isolates the master logic from the streaming logic.

I hope that makes sense.