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Altera_Forum
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13 years ago

Logic Analyzer Interface (LAI) destroys my design

Hi everyone! I have the following problem: I made a design with PCIe, I²C, SPI and a SRAM-Memory. The I²C- and SPI-Cores are made by myself and connected to the PCIe HIP with some PIOs. The...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Red paths are the ones that dont meet the timing specs specified. Usually this means investigating and adding more pipelining or doing some other funky constraining (but the pipelining is usually the easiest).