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OK, so I now have it properly addressing with 64 bit addresses, but there is a problem with actually verifying data transfer. I can DMA a block of data to it, for example the following is part of a PCIe analyzer trace for a 256byte transfer. The first two TLP's are reads from the RC and show the correct data which is a simple incrementing pattern..
TLP 1
05550000 05550001 05550002 05550003 05550004 05550005 05550006 05550007 05550008 05550009 0555000A 0555000B 0555000C 0555000D
TLP 2
0555000E 0555000F 05550010 05550011 05550012 05550013 05550014 05550015 05550016 05550017 05550018 05550019 0555001A 0555001B 0555001C 0555001D 0555001E 0555001F
But when I read it back using DMA, the data is corrupted..
05550000 05550001 05550002 05550003 05550004 05550005 05550006 05550007 05550008 05550009 0555000E 0555000F 05550010 05550011 05550012 05550013 05550014 05550015 05550016 05550017 05550018 05550019 0555001A 0555001B 0555001C 0555001D 0555001E 0555001F 00000000 00000000 00000000 00000000
The ones highlighted in RED show where the errors start. Basically the 11th value which should be 0555000A is actually 0555000E. 0555000A - 0555000D are missing. It almost looks like the data starting at 0555000E overwrote it at the wrong spot as if it had a bug incrementing the internal memory address.
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I am having a similar problem with the 64 bit PCIe ref design on a Stratix IV GT FPGA. I wonder if you have had a solution for it. It seems to me that the problem is related to the Avalon-ST interface between the PCIe hard IP core and the application on endpoint.
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