Forum Discussion
Altera_Forum
Honored Contributor
16 years agoI had a similar issue and found that the reference design DMA hardware has a parameter set that causes it to assume 32-bit addressing, and thus, always generates 3DW headers. I worked around the issue by changing the parameter RC_64BITS_ADDR in altpcierd_example_app_chaining.v from 0 to 1. After rebuilding the h/w in Quartus, I observed 4DW headers where required.
I hope this helps.