Honored Contributor
Honored ContributorThank you so much GZoinker ,
Do I load the license file correctly ? I load it from tools - license setup section and after loading license file ,when compile the project I see "Can't generate netlist output files because the file <file name> is an OpenCore Plus time-limited file" I think the license problem is seen as unsolved.Is there another way to solve that problem, I read installation and licensing manual but I couldn't solve maybe Addition to this,Altera says title [h=1]Error: Can't generate netlist output files because the file <file name> is an OpenCore Plus time-limited file[/h]description You may see this error when compiling your design using the Quartus® II software if your design contains one or more unlicensed cores operating in OpenCore Plus mode and you have enabled an EDA simulation tool in your Quartus II project. workaround / fix To avoid this error, disable the EDA simulation tool in your project by opening the settings dialog box from the Quartus II Assignments menu. Select the category eda tool settings and the subcategory simulation. On the simulationpage of the settings dialog box, change the tool name option to <none>. That means I can't simulate this IP core but ıt works without any problem.Am I right ? Also there is a warning and I can't understand what it says well Warning (265069): Megafunction that supports OpenCore Plus feature will stop functioning in 1 hour after device is programmed Do The following messages show that the pci_t32 will work fine ? Warning (12188): OpenCore Plus Hardware Evaluation feature is turned on for the following cores Warning (12190): ""PCI Compiler" (6AF7_0024)" will use the OpenCore Plus Hardware Evaluation feature Warning (265072): Messages from megafunction that supports OpenCore Plus feature Warning (265073): Messages from megafunction that supports OpenCore Plus feature pci_t32 Warning (265074): The pci_t32 idsel will be disabled when the evaluation time expire Warning (265074): The pci_t32 memory bar hit will be disabled after time-out is reached I have write several programs with different FPGA but I have never used an IP Core before,So I really need help.Thanks in advance for your help,
