LF LFSR simulation get zero values in DSP Builder

Try a simple code first, like outputting a constant value, and see what you get in Matlab. That way you will know if the problem comes from the code or the export function to Matlab. I've never worked with DSP builder in conjunction with Matlab so I can't help you further.

Your loop is rather strange... It looks like you are trying to write a software algorithm in HDL, and it won't work that way. One important thing about VHDL signals is that when you do a <= assignment in a process, the signal will only get the new value after the process is completed and only the last assignment done on a signal is actually taken into account. This means that:[list]

[*] the line temp_sr(n) <= temp_sr(n+1); is useless, as the value is overwritten in the following lines

[*] the loop is useless, because you are just doing 13 times the same thing[/list]

I suggest first thinking about how this LFSR function would be done in hardware, and then write some HDL code that describes it.