LAB Optimization

I have quartus 12.1sp1. This is my Resource Usage Report:

ALUTs Used 36,124 / 50,600 ( 71 % )

-- Combinational ALUTs 36,124 / 50,600 ( 71 % )

-- Memory ALUTs 0 / 25,300 ( 0 % )

-- LUT_REGs 0 / 50,600 ( 0 % )

Dedicated logic registers 5,962 / 50,600 ( 12 % )

Combinational ALUT usage by number of inputs

-- 7 input functions 347

-- 6 input functions 21009

-- 5 input functions 4256

-- 4 input functions 4482

-- <=3 input functions 6030

Combinational ALUTs by mode

-- normal mode 34318

-- extended LUT mode 347

-- arithmetic mode 1249

-- shared arithmetic mode 210

Logic utilization 58,120 / 50,600 ( 115 % )

-- Difficulty Clustering Design No-Fit

-- Combinational ALUT/register pairs used in final Placement 37044

-- Combinational with no register 31082

-- Register only 920

-- Combinational with a register 5042

-- Estimated pairs recoverable by pairing ALUTs and registers as design grows 0

-- Estimated Combinational ALUT/register pairs unavailable 21076

-- Unavailable due to Memory LAB use 0

-- Unavailable due to unpartnered 7 LUTs 347

-- Unavailable due to unpartnered 6 LUTs 20553

-- Unavailable due to unpartnered 5 LUTs 34

-- Unavailable due to LAB-wide signal conflicts 20

-- Unavailable due to LAB input limits 65

-- Unavailable due to location constrained logic 1

Total registers* 5962

-- Dedicated logic registers 5,962 / 51,336 ( 12 % )

-- I/O registers 0 / 2,232 ( 0 % )

-- LUT_REGs 0

ALMs: partially or completely used 29,001 / 25,300 ( 115 % )

Total LABs: partially or completely used 2,906 / 2,530 ( 115 % )

-- Logic LABs 2,906 / 2,906 ( 100 % )

-- Memory LABs 0 / 2,906 ( 0 % )

Virtual pins 0

I/O pins 82 / 404 ( 20 % )

-- Clock pins 0 / 10 ( 0 % )

-- Dedicated input pins 0 / 28 ( 0 % )

Global signals 17

M9K blocks 64 / 495 ( 13 % )

Total MLAB memory bits 0

Total block memory bits 125,984 / 4,561,920 ( 3 % )

Total block memory implementation bits 589,824 / 4,561,920 ( 13 % )

DSP block 18-bit elements 0 / 312 ( 0 % )

PLLs 1 / 4 ( 25 % )

Global clocks 16 / 16 ( 100 % )

Quadrant clocks 0 / 48 ( 0 % )

Periphery clocks 0 / 50 ( 0 % )

SERDES receivers 0 / 28 ( 0 % )

JTAGs 0 / 1 ( 0 % )

ASMI blocks 0 / 1 ( 0 % )

CRC blocks 0 / 1 ( 0 % )

Remote update blocks 0 / 1 ( 0 % )

GXB Receiver channel PCSs 1 / 8 ( 13 % )

GXB Receiver channel PMAs 1 / 8 ( 13 % )

GXB Transmitter channel PCSs 1 / 8 ( 13 % )

GXB Transmitter channel PMAs 1 / 8 ( 13 % )

HSSI CMU PLLs 1 / 4 ( 25 % )

Impedance control blocks 0 / 3 ( 0 % )

Maximum fan-out 3662

Highest non-global fan-out 1696

Total fan-out 221200

Average fan-out 5.12