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JQ2's avatar
JQ2
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5 years ago

JESD204C IP with shared PHY

For JESD204C IP, I would like to use TX 8 lanes and RX 4 lanes. Can I instantiate two IPs, one with TX-only (Both Base and PHY) and the other one is RX-only (also Both Base and PHY) and then both IPs...
CheepinC_altera's avatar
CheepinC_altera
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5 years ago

Hi,

As I understand it, you have some inquiries related to the simplex merging of the JESD204C IP. As I search through the user guide, I am unable to locate any specific info on this. Based on the understanding from JESD204B IP, ideally you should be able to perform simplex merging. However, simplex merging is allowed when both of the simplex instances are of same number of lanes ie TX 4 lanes and RX 4 lanes.

It is also recommended for you to create simple test design in Quartus and run through Fitter compilation to check against internal placement rules.

Please let me know if there is any concern. Thank you.


Best regards,
Chee Pin

JQ2's avatar
JQ2
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5 years ago

Hi Mr. Pin,

Regarding simplex merging of PHY, I found this document (https://www.intel.com/content/www/us/en/programmable/documentation/wry1479165198810.html#meo1484178883065). However, this one is regarding NATIVE PHY.

Q1: Since we want to merge PHYs for JESD204C use, can we use 1) JESD204C IP with PHY-only option, or we must use 2) transceiver NATIVE PHY IP, which is a more general PHY IP?

Q2: If the answer is yes, then in the above document, it says "You cannot merge the TX and RX channels when the Shared reconfiguration interface parameter is enabled in the Native PHY IP core Parameter Editor". However, in JESD204C IP with PHY-only option, there is no such option. Does it mean I should instantiate multiple IPs with 1 channel per IP? For example, if I want to merge 2 TX and 2 RX, I need to instantiate 4 JESD PHY IPs, 2 channels for TX (TX0, TX1) and 2 for RX (RX0, RX1). Then merge TX0 and RX0 under mm_bridge_0, merge TX1 and RX1 under mm_bridge_1? Is this correct?

Q3: Does the E-Tile Transceiver PHY support merging? Because here (page 37 of https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_jesd204b.pdf ), it says "For simplex variants with E-tile transceiver, the underneath transceiver is in duplex mode. The merging of independent TX and RX within a transceiver channel is not supported in this version", but in E-Tile Transceiver UG, I could find any reference.

Thank you for your help. @CheePin_C_Intel

Regards,

Junqian