Forum Discussion
Amirg
New Contributor
6 years agoJesd204b interface seems to misbehave after upgrading quartus from 16 to 19
Hi, i have a design with jesd204b interfacing adc device, but after upgrading to quartus 19.2, the sync signals seems to assert and deassert all the time. i re-generated all of the ip's. what coul...
CheepinC_altera
Regular Contributor
6 years agoHi,
Thanks for your update. I have taken a look into the signaltap that you shared. I can see that the rx_dev_sync_n seems to be de-asserted which trigger a new round of link initialization. The lane alignment achieved but after sometime, the rx_dev_sync_n seems to be de-asserted again. From the signaltap, I could not spot any anomaly which could lead the rx_dev_sync_n de-assertion.
It could be either an unexpected reset to the IP or the XCVR lose lock. To facilitate further debugging, would you mind to add the following signals to the SignalTap to check on RX PHY:
rx_is_lockedtoref
rx_is_lockedtodata
rx_analogreset
rx_digitalreset
rx_analogreset_stat
rx_digitalreset_stat
rx_cal_busy
Please let me know if there is any concern. Thank you.