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Amirg's avatar
Amirg
Icon for New Contributor rankNew Contributor
5 years ago

Jesd204b interface seems to misbehave after upgrading quartus from 16 to 19

Hi, i have a design with jesd204b interfacing adc device, but after upgrading to quartus 19.2, the sync signals seems to assert and deassert all the time. i re-generated all of the ip's. what coul...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

Thanks for your update. I have sent you an email.

Regarding the unable to lock to refclk issue, just would like to check with you which specific signals are you monitoring to tell unable to lock to refclk?

Regarding the issue seems to be resolved after ON/OFF the boards a few times, the following are a few possible causes:

1. Signal integrity issue - you might need to further look into the refclk signal input to the FPGA pin to ensure it is meeting the refclk input requirement as in the datasheet. You can probe the signal using oscilloscope.

2. refclk - It would be great if you could check the signal using oscilloscope when issue occurs to check on the frequency. This is to ensure the frequency is correct and stable.

3. power up calibration - refclk need to be stable and free-running. The refclk should be stable before device power up to ensure power up calibration is completed successfully.

Please keep me posted on the loopback test in the Modelsim for single duplex instance.

Thank you.