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Amirg's avatar
Amirg
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5 years ago

Jesd204b interface seems to misbehave after upgrading quartus from 16 to 19

Hi, i have a design with jesd204b interfacing adc device, but after upgrading to quartus 19.2, the sync signals seems to assert and deassert all the time. i re-generated all of the ip's. what coul...
Amirg's avatar
Amirg
Icon for New Contributor rankNew Contributor
5 years ago

Hi again,

sorry for the delay..

  1. as for the modelsim simulation, its a work in progress. there's should be something ready here, im looking for it for further testing.
  2. rx_is_lockedtodata is at 'F', all the rest at '0' (to be exact, there are two jesd rx items in this design, one of them somtimes fails to lock to ref clock. turning the board on and off a few time seems to solve this issue for now)
  3. please send me a mail, i got the qsys and signal tap of the "link initialization" from figure 33 to transfer to you.

Thanks