Jesd204b interface seems to misbehave after upgrading quartus from 16 to 19

Hi,

the device is Arraia 10.

once i was going through the signals in signal tap and on the timing constraints described in the jesd204b ip pdf file, i noticed that the signals "rx_is_lockedtoref" droppes every now and then for at least one of the lanes (could change after shutting off and back of the device). after making sure the constraints match the definitions in the pdf file (put them in a different clock group) and re-apply some attributres ("set_global_assignment GLOBAL_SIGNAL GLOBAL_CLOCK" on several clocks, including those from the jesd204 pll ip) rx_is_lockedtoref seems to be stable at "f" (all ones)

the issue im seeing now, is that still, dev_sync_n signals drops for about 50 clocks all the time, after that the signals alldev_lane_aligned, dev_lane_aligned and jesd204_rx_link_valid deasserts one after the other for some reason.

as much as i know this is not the right behaviour for my setup.

ill see if i can get the qsys or signaltap image out, but chances are slim. for qar there's no chance at all. anyway - this may take a while.

any thuoghts so far? is there any other thing i can test ?

Thanks.