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Amirg's avatar
Amirg
Icon for New Contributor rankNew Contributor
5 years ago

Jesd204b interface seems to misbehave after upgrading quartus from 16 to 19

Hi, i have a design with jesd204b interfacing adc device, but after upgrading to quartus 19.2, the sync signals seems to assert and deassert all the time. i re-generated all of the ip's. what coul...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

Thanks for your update. Please see my responses as following:

1. Mind let me know which FPGA device that you are using to interface with the ADC?

2. When you refer to sync signal toggling, mind let me know which specific sync signal that you are referring to ie from the JESD204B IP?

3. For the screenshot, signaltap and .qsys or QAR file, you may send through email to me if there is any concern posting it to the Forum. I will send you an email and your may reply to that. Please share with me further on the issue observation so that I can have a better understanding on your sync issue.

4. As for the Modelsim simulation, it is recommended for you to perform a loopback using duplex mode JESD204B IP to further narrow down the issue. If issue occur even with loopback, then we could isolate the external device.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin